Study of Static Power of Clocked Pair Shared Flip Flop For Low Power Clocking System

In the past, the major issue of the VLSI designer were area, cost, performance, and reliability; power consideration was mostly of only inferior importance. But over the last few years power in the circuit is the major problem now days which is being faced by the very large scale integration industries. The power dissipation in any circuit is usually take place by the clocking system which includes the clock distribution system and sequential elements (flip flops and latches) in it. The amount of power dissipation by any clock distribution system and sequential circuit in any chip is about of 30% to 60% of the total chip power dissipation by the circuit. Clock is the most important signal present in the chip. Clock signals are synchronizing signals which provide timing references for computation of any work in synchronous digital systems. In this paper the static power of the clocked pair shared flip flop of the clocking system is surveyed with the help of the H spice software.